Browse Prior Art Database

Improved Full Wafer Process

IP.com Disclosure Number: IPCOM000045355D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Faris, SM: AUTHOR

Abstract

This article relates generally to the fabrication of Josephson junctions and more particularly to the fabrication of Josephson junctions using a full-wafer process with a reduced number of masks.

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Improved Full Wafer Process

This article relates generally to the fabrication of Josephson junctions and more particularly to the fabrication of Josephson junctions using a full-wafer process with a reduced number of masks.

Fig. 1 shows the first step in the fabrication of Josephson junctions using a full-wafer process. Fig. 1 does not show the silicon substrate on which the various layers are formed, but its presence should be assumed. In Fig. 1, layers M1, M2 and M3 are niobium or some other suitable superconductive metal well known to those skilled in the Josephson art. The layers between M2 and M1 and between M2 and M3 are oxides of niobium, for example. The oxide layer between layers M2 and M3 is sufficiently thin to permit tunnelling between layers M2 and M3.

Fig. 2 shows layers M2 and M3 and their intervening tunnel barrier after small junctions have been defined by well-known photolithographic and etching techniques. A photoresist layer (not shown) on layer M3 acts as a mask during etching.

Fig. 3 shows the arrangement of Fig. 2 after it has been subjected to a plasma oxidation step in the presence of a photoresist layer PR. Regions of plasma-grown oxide approximately 500 Angstrom thick are formed on the exposed edges of layers M2 and M3.

Fig. 4 shows a Josephson junction after a contact region to the M2 layer has been defined, again using well-known photolithographic and etching techniques. As a result of this, a portion of the M2 layer has been exposed....