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Superconducting Driver and Shift Register

IP.com Disclosure Number: IPCOM000045356D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR

Abstract

Two identical Josephson junction interferometers, separately controlled so that one or the other is in the voltage state at any given time, provide a DC-powered inverting chip-to-chip driver which avoids the punchthrough problem. Separate even-odd voltage driver and intermediate transfer mechanisms provide direct interstage transfer in a shift register.

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Superconducting Driver and Shift Register

Two identical Josephson junction interferometers, separately controlled so that one or the other is in the voltage state at any given time, provide a DC- powered inverting chip-to-chip driver which avoids the punchthrough problem. Separate even-odd voltage driver and intermediate transfer mechanisms provide direct interstage transfer in a shift register.

The driver circuit is shown in Fig. 1. "A" is a junction voltage source with a resistive load across it. The junction is biased in the voltage state at the gap. "B" and "C" are two identical interferometers that can be separately controlled by signals S1 and S2 on lines 1 and 2, respectively. Either "B" or "C" is in the voltage state at any given time. A matched transmission line that carries a signal from chip to chip (Z=R) is connected across "C." The resistors R, r, and the bias voltage of "A" determine the current through "B" and "C."

At the beginning of a cycle, interferometer "C" is switched into the voltage state 1 by a set pulse (S1) on line 1, transferring current into the driver line 3. Later, the signal arrives at "B," switching it into the voltage stage. Men the gate "B" switches, the voltage across "C" is reduced below V (min) (resetting voltage) and "C" goes into the zero-voltage state.

Fig. 2 is an I-V chart showing the load-line trajectories. The bias voltage V of "A" and resistor R and r are chosen such that.

Fig. 3 shows a five-stage shift register application. The shift register includes, for each stage, a two-junction interferometer (A(1)-A(5)), and a single junction (B(1)-B(5)). The circuit is biased with a constant DC voltage V(DC). I...