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CMOS Sense Restore Ciruits for One Device FET Dynamic RAM

IP.com Disclosure Number: IPCOM000045360D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+2]

Abstract

This publication describes CMOS (complementary metal oxide semiconductor) sense-restore circuits for use with one-device FET (field effect transistor) dynamic RAMs (random-access memories). The schematic circuit diagram used for memory cells with p-channel MOSFET transfer devices is shown in Fig. 1. The operating waveforms for the circuit of Fig. 1 are shown in Fig. 2. The operation of the circuit of Fig. 1 is as follows.

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CMOS Sense Restore Ciruits for One Device FET Dynamic RAM

This publication describes CMOS (complementary metal oxide semiconductor) sense-restore circuits for use with one-device FET (field effect transistor) dynamic RAMs (random-access memories). The schematic circuit diagram used for memory cells with p-channel MOSFET transfer devices is shown in Fig. 1. The operating waveforms for the circuit of Fig. 1 are shown in Fig. 2. The operation of the circuit of Fig. 1 is as follows.

Step 1) At standby signal, Phi(RS) (the dummy cell restore clock signal) is kept high to reset the storage node at N1 to ground.

The signal Phi(PC) (the precharge clock signal) is kept low to precharge bit lines BL1 and BL2 to V(DD). The Phi signal is kept at several V(T,n) above V(DD) to allow the internal nodes N2 and N3 of the sense amplifiers to become precharged to V(DD) and node N4 to become precharged to V(DD)-V(T,n) where V(T,n) is the threshold voltage of the n-channel MOSFET. The potential at node N5 is V(DD) + V', where V' < V(T,p) and V(T,p) is the threshold voltage of the MOSFET. Nodes N4 and N5 are common for all sense amplifiers in an array. Capacitor C3 is provided such that when Phi(PC) rises to V(DD) at the end of the precharge cycle, capacitor C3 boosts node N4 to ensure that T8 and T9 are in the cut-off state.

Assume for the purpose of illustration that a memory cell with a "0" stored is to be read, thus the potential at node N6 is at ground level. The operation for a stored "1" is analagous.

Step 2) The selected wordline (WL) and the selected dummy cell wordline (WL') fall to turn on the transfer FETs T3 and T12 to allow the charge sharing between each bitline and its associated memory cell or dummy cell. Since the bitlines are the sources of the transfer FETs, the charge sharing can be completed momentarily after the word line potential falls below V(DD)- V(T,p). Thus the wordline delay should be much shorter than that of the coventional sense-restore circuits. The potential at node N2 is V(DD) -Delta V/2 , and at node N3 it is V(DD) -Delta V.

Step 3) Signal Phi goes low (approx. V -V ) to temporarily isolate the internal nodes of the sense amplifier.

Step 4) The bootstrap...