Browse Prior Art Database

External Programmed Control of Random Logic

IP.com Disclosure Number: IPCOM000045370D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 42K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+3]

Abstract

The described control mechanism allows programmed control of various operating modes of random logic. An external computer can completely control the operation of logic including the selection of data paths and the supply of control signals.

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External Programmed Control of Random Logic

The described control mechanism allows programmed control of various operating modes of random logic. An external computer can completely control the operation of logic including the selection of data paths and the supply of control signals.

Random logic can take on multiple modes of operation (can be 'programmed') if its data paths and control signals are variable. An external signal source can set latches and registers to control the data paths in the random logic. It can also supply control signals. A general method will now be described on how a computer can exercise external control of random logic.

Random logic can operate in various modes and select input data from various sources. The following techniques can achieve this: - multiplexers select data and control signals, - multiplexers select data paths for input and output of signals, - mask registers and comparison registers filter data, - latches enable, disable, and select functions, and - external control signals trigger special functions. The mode of operation of multiple-purpose random logic is specified by the contents of all control memory (latches, registers, etc.), also called the status of the logic.

All control memory of the logic implementation is connected to a Common Bus 10 through which the status can be set and read. Individual status variables are grouped for addressing purposes into Status Vectors of fixed length. There is defined for each physical unit of the logic implementation, for instance, each logic card 12, a set of Status Vectors containing all its control memory. The Card Address and the Vector Address together uniquely identify a Status Vector. The Common Bus connects all the Status Vectors to a Control Unit 14 that directs the read and write operations of the Status Vectors and issues the control signals. The Control Computer 16 exercises overall control over the system by issuing commands to the Control Unit. The Control Computer also sends and receives the control data.

This scheme of external programmed control of random logic requires the following components shown in Fig. 1: External Control Section 13 on each random logic card 12, Common Bus 10,
Control Unit 14,
Control Computer 16.

Each logic card 12 that is controlled externally has an

External Control Section 13 that contains the attachment (Fig. 2) of the card to the Common Bus 10. The External Control Section 13 performs the following functions: decode the command (Read, Write, Signal), decode the vector address, serialize and deserialize the data.

A Transfer Register serves as a buffer where the parallel - serial conversions of the signals are performed. Performing this conversion in the Status Vectors

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20 would disturb the status and, therefore, also the operation of the logic. On a Signal command, the Vector Address specifies the circuit...