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In System In Insolation Module Testing Design

IP.com Disclosure Number: IPCOM000045372D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 116K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

Subdividing the functions of logic within a large-scale integration module makes it feasible to test the module in-system in-isolation and eliminates the need for complex module test adapters to simulate the system for testing.

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In System In Insolation Module Testing Design

Subdividing the functions of logic within a large-scale integration module makes it feasible to test the module in-system in-isolation and eliminates the need for complex module test adapters to simulate the system for testing.

The principles and practices of the in-situ testability design, sometimes described as "on-wafer on-module testability design," have been used mainly for logic chips. In a large system, however, the capability of testing all the logic modules in-situ in isolation is extremely valuable, since -- together with the in-situ chip testability -- it makes the in-situ testability scheme completely sufficient for the system testing.

This design provides for this in-situ module testability, in most cases requiring very little additional hardware expenditure. This design consists of the following steps:
1) For each of the chips on a module, the paths, including

input (I), output (O) and circuit nodes (CN) which may be

latch driven (L) or latch related, may be designated

I(CN)(L), I(CN), O(L) and O(CN)

for making the In-situ Testability Design (ISTD(Ch)). For

in-situ testability of the chip, these each are divided into

two components: those (I/-/, O/-/) which are

carrier-connected to other chips

on the same module, and those (I*, O*) which are fillet-fed or

fillet-bound (see Fig. 1).
2) To make the ISTD(Ch) for each chip, the two sets of components

are used separately to provide for the initial-conditions

control (ICC) and test-results retention (TRR) needed;

i.e. , for ICC, O/L/-/ is used to feed

I /CN/-/and O (L)to feed I (CN) and for TRR,

O/CN/-/ is captured by using I/CN/L/-/ and

O(CN) by using I*(CN)(L).
3) In case there are not enough latches, then arrangements

of subdividing the functions to be tested into two or

more test-group...