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LSSD Compatible D Function Latch

IP.com Disclosure Number: IPCOM000045411D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Canova, FJ: AUTHOR [+3]

Abstract

A "D" type edge-sensitive latch circuit is provided in a level sensitive scan design (LSSD) implementation with a minimum of logic circuit overhead.

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LSSD Compatible D Function Latch

A "D" type edge-sensitive latch circuit is provided in a level sensitive scan design (LSSD) implementation with a minimum of logic circuit overhead.

The level sensitive scan design (LSSD) methodology is a logic circuit design methodology that greatly simplifies the testing and servicing of logic circuits formed on large-scale integration (LSI) circuit chips. This methodology is described in a paper by Eichelberger et al., entitled "A Logic Design Structure for LSI Testability" that appears at pages 462-467 of the 14th Design Automation Conference Proceedings, dated June, 1977. Unfortunately, the requirements for a "D"type edge sensitive latch are not directly supported by the LSSD methodology. Various combinations of LSSD shift register latches will give the edge-sensitive function, but most of these combinations are very costly in logic cell overhead when only the basic six-gate "D" function is required. This overhead is the direct result of the aderence to the LSSD design ground rules which require two nonoverlapping clocks to cycle all clock networks.

The circuit described herein provides the "D" type edge-sensitive function with only nine logic cells while adhering to the LSSD design ground rules. This circuit includes the clock isolation and scan functions required in an LSSD design and has been found to be 100 percent stuck-fault testable.

Fig. 1 shows the circuit construction and Fig. 2 shows some representative waveforms for the Fig. 1 circuit. Each of the L1 and L2 latch circuits is a polarity- hold latch circuit implemented by means of AND-INVERT logic gates. Typical forms of construction for these L1 and L2 latches are shown in the Eichelberger et al. paper.

The L1 and L2 latches operate in an alternate "hold/flush" mode through each transition of the +CLOCK signal. It is assumed that for normal circuit operations, as opposed to the LSSD scan mode operation, th...