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Browse Prior Art Database

LSSD Compatible Synchronous Incrementer

IP.com Disclosure Number: IPCOM000045412D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Canova, FJ: AUTHOR [+3]

Abstract

There is described a fast-loadable binary counter or incrementer which requires a minimum of logic overhead while adhering to level-sensitive scan design (LSSD) ground rules.

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LSSD Compatible Synchronous Incrementer

There is described a fast-loadable binary counter or incrementer which requires a minimum of logic overhead while adhering to level-sensitive scan design (LSSD) ground rules.

The LSSD technique and the construction of a typical shift register latch (SRL) used in implementing such technique are described by E. Eichelberger et al.) in a paper entitled "A Logic Design Structure For LSI Testability," published in the 14th Design Automation Conference Proceedings, June, 1977, pages 462- 467. In binary circuits constructed in accordance with such LSSD ground rules, there are at least two clocks common to all of the SRLs. The circuitry described herein uses this feature as part of a synchronous counter or incrementer in order to minimize the number of logic gates and still be LSSD-compatable with no untested faults.

Figs. 1A, 1B and 1C, when placed one above the other, show the six lower order stages of an N-stage binary incrementer. Each stage includes an SRL, and each SRL includes an L1 polarity-hold latch circuit connected to an L2 polarity-hold latch circuit in a master-slave relationship. The Bit 1 SRL shown in Fig. 1A is the least significant bit stage. A plural-bit binary number can be loaded into the incrementer stages in a parallel manner by way of data bit input lines DBI 1 through DBI 6, with DBI 1 being the least significant bit line. The output of the incrementer is available in parallel form on data bit out lines DBO 1 through DBO
6. The interstage carry signals, for example, the "-Carry 1-4" signal...