Browse Prior Art Database

Passive Divide Lookahead Circuit

IP.com Disclosure Number: IPCOM000045414D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR

Abstract

A carry save adder, such as that described in the U. S. Patent 4,110,832, is used to execute a high speed floating-point divide. Divide lookahead circuitry is described that uses fewer logic circuits, that is significantly faster in operation, and that simplifies the microcode in relation to prior circuits of this nature such as that set forth in the U.S. Patent 4,084,254.

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Passive Divide Lookahead Circuit

A carry save adder, such as that described in the U. S. Patent 4,110,832, is used to execute a high speed floating-point divide. Divide lookahead circuitry is described that uses fewer logic circuits, that is significantly faster in operation, and that simplifies the microcode in relation to prior circuits of this nature such as that set forth in the U.S. Patent 4,084,254.

A divide is performed by shifting the remainder left and subtracting the divisor, if the divisor is smaller than the shifted remainder. The corresponding quotient bit is equal to 1 if a subtract is performed and 0 if there is no subtraction (Divisor J Shifted Remainder).

The divide lookahead circuitry is used to determine if the shifted remainder (which is stored in the Carry Save Adder as Carry and Sum Bits) is larger than the divisor before the result of the subtraction is stored.

Referring to the drawings, the remainder is stored in the Carry Save Adder in complement form. This allows for fast subtractions. Since one operand has already been complemented, only an addition must be performed. However, because the remainder is stored as sum bits (S) and carry bits (C), the carries must be propagated after the subtraction to determine the true result.

The divide lookahead circuitry propagates the Presum (PS) and Precarry (PC) bits that are generated when the divisor is added to the complemented and left-shifted remainder. If the divisor (D) is smaller than the shifted remainder, the result will remain negative and there will be no carry out.

The Presums and Precarries for the shift left and add can be generated as follows: PS(A)=S(0)+C(1)

PS(0)=S(1) 0+ C(2) 0+ D(0)

PC(0)=(S(1) - C(2)) + (S(1) . D(0)) + (C(2) . D(0))

In general,

PS(N)=S(N+1) + C(N+2) 0 D(N)...