Browse Prior Art Database

Pseudo Full Duplex Communications Between a Data Processor and an I/O Device Adapter

IP.com Disclosure Number: IPCOM000045419D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Bhansali, MM: AUTHOR [+3]

Abstract

A mechanism is described which enables pseudo full duplex communications between an IBM Series/1 data processor and an I/O device adapter which recognizes only a single-device address. More particularly, this mechanism enables data to be transferred from the I/O adapter to the processor during a cycle steal data transfer operation wherein the system is busily engaged in transferring multiple bytes or words of data from the processor to the I/O adapter in a cycle steal mode.

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Pseudo Full Duplex Communications Between a Data Processor and an I/O Device Adapter

A mechanism is described which enables pseudo full duplex communications between an IBM Series/1 data processor and an I/O device adapter which recognizes only a single-device address. More particularly, this mechanism enables data to be transferred from the I/O adapter to the processor during a cycle steal data transfer operation wherein the system is busily engaged in transferring multiple bytes or words of data from the processor to the I/O adapter in a cycle steal mode.

Heretofore, single-device address adapters have been used only in either a receive (adapter to processor) mode or a transmit (processor to adapter) mode. In various situations, however, it would be desirable to be able to transfer data from the adapter to the processor while the processor is engaged in executing a transmit (processor to adapter) mode cycle steal command. In the more recent Series/1 I/O adapters, it is possible for the adapter to send an interrupt request to the processor during the execution of a cycle steal data transfer command and it impossible for the processor to attempt to respond to such interrupt request by attempting to send a new I/O command to the adapter. Such an attempt would fail, however, because the adapter would report back a "Device Busy" condition by way of the Condition Code In bus. The processor would then put the new I/O command in a queue and would await completion of the execution of the cycle steal command before attempting to retransmit the new command. Thus, if a cycle steal transmit command is in progress and the adapter should receive data from the I/O device, it could notify the processor that it had data to send to it, but such data could not be transferred to the processor until after completion of all of the data transfers for the cycle steal command. Thus, only a half duplex mode of operation could be attained.

The new technique which is the subject of this paper gets around this limitation by using the interrupt request mechanism not only to notify the processor of the desire to send it data but also for actually sending the data to the processor. In the Series/1 architecture, when an interrupt request on the Interrupt Request In bus is accepted by the processor, an interrupt identification word is immediately thereafter transferred to the processor via the Data bus and a condition code describing the nature of the interrupt request is reported by way of the Condition Code In bus. One byt...