Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Improved I/O Channel Utilization for Pseudo Full Duplex Data Communications Between a Data Processor and and I/O Adapter

IP.com Disclosure Number: IPCOM000045420D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Bhansali, MM: AUTHOR [+3]

Abstract

A mechanism is described for improving the I/O channel utilization for a full duplex cycle stealing I/O device having only a single-device address. This mechanism makes available additional channel bandwidth for other I/O devices and enables the implementation of a full duplex-like capability using a single-device address I/O adapter. This mechanism will be described for the case of an IBM Series/1 data processor and its I/O channel.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Improved I/O Channel Utilization for Pseudo Full Duplex Data Communications Between a Data Processor and and I/O Adapter

A mechanism is described for improving the I/O channel utilization for a full duplex cycle stealing I/O device having only a single-device address. This mechanism makes available additional channel bandwidth for other I/O devices and enables the implementation of a full duplex-like capability using a single- device address I/O adapter. This mechanism will be described for the case of an IBM Series/1 data processor and its I/O channel.

In the past, full duplex I/O adapters have been implemented to respond to two different device addresses for purposes of enabling the simultaneous transmission and reception of data to and from an I/O device. One device address is used for transferring data from the processor to the I/O adapter, while the other device address is used for transferring data in the opposite direction, namely, from the adapter to the processor. In various situations, it is desired that these data transfers be done on a character by character basis. This is especially true when the I/O device is a keyboard display terminal where character substitution, positive feedback and better human factors are required.

If both the receive (device-to-processor) and subsequent transmit (processor- to-device) operations are only performed in a cycle stealing mode, then for the case of a Series/1 processor the normal steps for receiving and transmitting a character in full duplex mode would be as follows: (1) issue a Start I/O command for receive, (2) transfer a 16 byte device control block (DCB) from the processor to the I/O adapter, (3) transfer one byte of data, (4) interrupt with a Device End condition code, (5) issue a Start I/O command for transmit, (6) transfer a 16-byte device control block (DCB) from the processor to the I/O adapter, (7) transfer one byte of data, and (8) interrupt with a Device End condition code. This technique has been tested in various applications and shows extreme channel loading and severe band rate limitations.

The mechanism described herein uses up to 18 fewer word transfers and one less Start I/O instruction for every character received a...