Browse Prior Art Database

Patch Mechanism for a Multiprocessor System

IP.com Disclosure Number: IPCOM000045453D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Buonomo, JP: AUTHOR [+4]

Abstract

In a multimicroprocessor system, where one or more of the microprocessors (MPUs) are provided with and utilize on-chip microcode, it is possible and advantageous to bypass faulty microcode until a permanent fix therefore is implemented. Such a capability is particularly useful in a microprocessor system that is utilizing microcoded MPUs to emulate a main frame instruction set.

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Patch Mechanism for a Multiprocessor System

In a multimicroprocessor system, where one or more of the microprocessors (MPUs) are provided with and utilize on-chip microcode, it is possible and advantageous to bypass faulty microcode until a permanent fix therefore is implemented. Such a capability is particularly useful in a microprocessor system that is utilizing microcoded MPUs to emulate a main frame instruction set.

Faulty on-chip microcode is bypassed by employing "monitoring hardware" that "watches" instructions as they are fetched from storage and relayed to an MPU. When the instruction(s) watched for enter the system, the monitoring hardware signals the fetching MPU that the fetch has resulted in a main storage error.

As a result of this main storage error, the fetching MPU passes control to the system's error MPU normally, that is, the specific MPU having the responsibility for and capability of handling errors of this type. The system error MPU then determines and emulates the failing instruction, bypassing the faulty on-chip microcode. After emulation is completed, control is returned to the instruction fetching MPU, whereupon error-free processing is continued. The system error MPU must have off-chip microcode made available thereto so that it can effect a temporary patch to emulate the failing instruction(s). A permanent patch of the faulty microcode would thereafter be made in response to recognition of the emulated patch that did take place.

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