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Instruction Retry Mechanism for a Multimicroprocessor System

IP.com Disclosure Number: IPCOM000045455D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Buonomo, JP: AUTHOR [+4]

Abstract

The instruction retry mechanism described herein consists of an instruction retry latch and a protocol between all microprocessors in the system. The instruction retry latch is set on power-up, on system reset or whenever there has been a successful instruction fetch from main storage. The instruction retry latch is reset whenever there has been an operand write and a successful write indication from main storage.

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Instruction Retry Mechanism for a Multimicroprocessor System

The instruction retry mechanism described herein consists of an instruction retry latch and a protocol between all microprocessors in the system. The instruction retry latch is set on power-up, on system reset or whenever there has been a successful instruction fetch from main storage. The instruction retry latch is reset whenever there has been an operand write and a successful write indication from main storage.

To make the instruction retry mechanism work, the protocol that must be observed by all microprocessors in the system is simple. No architected facility, such as the general purpose or floating point registers, can be partially altered by any instruction. All microprocessors must also categorize all internal errors, so that they invoke the system retry handler only when positive that architected facilities are unaltered.

When the system retry handler is invoked, an instruction retry may be attempted, if the instruction retry latch is set. This is possible because the instruction retry latch and the protocol insure that all architected facilities are as they were at the beginning of the instruction.

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