Browse Prior Art Database

Chip on Chip Module for Assembly

IP.com Disclosure Number: IPCOM000045461D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Spector, CJ: AUTHOR [+2]

Abstract

This chip-on-chip interconnection technique uses tab bonding or solder-ball bonding or back bonding, at the option of the designer, to connect the 'master' chip to the module. However, the slave chip always is directly connected to the master chip via-solder ball bonding. The direct solder-ball interconnections between chips introduce minimal delay, eliminate the need for external driver-receiver circuits for interconnections between chips and avoid thermal mismatch problems.

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Chip on Chip Module for Assembly

This chip-on-chip interconnection technique uses tab bonding or solder-ball bonding or back bonding, at the option of the designer, to connect the 'master' chip to the module. However, the slave chip always is directly connected to the master chip via-solder ball bonding. The direct solder-ball interconnections between chips introduce minimal delay, eliminate the need for external driver- receiver circuits for interconnections between chips and avoid thermal mismatch problems.

In Fig. 1, heat is readily removed through the module cap 1 from the larger master chip 2 via the thermal grease 3. Spring 4 presses slave chip 5 towards cap 1. Slave chip 5 is connected to master chip 2 by solder balls 6. Chip 1 is connected to the module substrate 7 by tabs 8. The only silicon-to-ceramic connection is made via the flexible tabs 8 so that heat-induced mechanical stresses are avoided in the assembly.

The Fig. 2 simplification of Fig. 1 omits the spring 4, thermal grease 3 and cap 1. Instead, module substrate 7' is etched to provide recess 9 for receiving slave chip 5'. Chip 5' is face-to-face connected to master chip 2' via solder balls 6'. Additionally, master chip 2' is connected to substrate 7' by those solder balls 6' which lie outside the perimeter of slave chip 5'.

In Fig. 3, the master chip 2" is back-bonded to substrate 7". Electrical connection to the substrate is made via tabs 8". Slave chip 5", as before, is connected to master ch...