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Improved Buried Channel Charge Coupled Device Array Using Double Polysilicon

IP.com Disclosure Number: IPCOM000045466D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Carballo, RA: AUTHOR [+4]

Abstract

This is a serial-parallel-serial (SPS) charge-coupled device (CCD) shift register, using a total of three serial-parallel transfer clocks, and an improved charge launcher for charge inputting to the input serial register. This is accomplished without the use of the midway store clocking found in most charge-coupled SPS configurations. A 32x128-bit organization with an interlaced four-phase multiplexed electrode per bit SPS is shown in Fig. 1, by way of example.

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Improved Buried Channel Charge Coupled Device Array Using Double Polysilicon

This is a serial-parallel-serial (SPS) charge-coupled device (CCD) shift register, using a total of three serial-parallel transfer clocks, and an improved charge launcher for charge inputting to the input serial register. This is accomplished without the use of the midway store clocking found in most charge- coupled SPS configurations. A 32x128-bit organization with an interlaced four- phase multiplexed electrode per bit SPS is shown in Fig. 1, by way of example.

The Charge Launcher. The charge launcher, as illustrated in Fig. 2, is based on a buried channel charge coupled device. The launcher circuit interacts with three key device regions if the input shift register. These consist of the N diffused node of V , the P+ ion-implanted transfer well TG, located near the N+ regions, and the N+ ion implanted storage well SG, located immediately next to the transfer gate TG. The configuration shown in Fig. 2 provides significantly improved charge launching. The three-transistor network (T1, T2, T3), controlling the V(ID) potential to one threshold below the power supply V(DD), provides a new voltage level for the fill and spill operations of the input serial register.

During a charge launching cycle (to fill), the V(ID) potential is kept at a constant potential level lower than the well potential of the first transfer Rate (TG) when V(SIG) is pulsed high. Therefore, the initial charge packet is made to safely fill the first storage well SG. However, the charge packet in the storage well SG is to be metered during the charge spill process of the launching cycle, since the transfer gate TG pulse level is now at its lower potential. The input network will now compensate for ion-implant processing variations under the transfer gate, and result in an effective charge launching which will be less sensiti...