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Serial Parallel Serial CCD Loop with Merged Transfer Output Gate

IP.com Disclosure Number: IPCOM000045467D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Carballo, RA: AUTHOR [+3]

Abstract

This is a charge output technique using a merged charge transfer gate from the parallel register to the output serial register of a serial parallel serial (SPS) charge-coupled device (CCD) register.

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Serial Parallel Serial CCD Loop with Merged Transfer Output Gate

This is a charge output technique using a merged charge transfer gate from the parallel register to the output serial register of a serial parallel serial (SPS) charge-coupled device (CCD) register.

The SPS CCD structure per se is a well-known charge storing element. In Fig. 1, a simplified 4K SPS single gate organization is shown. A single charge input transfer gate (OTIN) is adequate for moving the charge packets from the input serial register 10 to the parallel section 12 of the SPS CCD. The input register 10 holds an even amount of charge 2 under the 01 and B2 storage gates, as shown in Fig. 1. The sense amplifier I/O interface and charge launcher are conventional for this configuration.

Fig. 2 is a timing diagram illustrating the operation of the Fig. 1 organization. Clock pulses 01 and 02 are applied to the input and output serial registers. Clock pulses OTIN and OP are used at the interface regions. The other clock pulses (OP1-OP8) are standard eight-phase electrode per bit pulses for transferring charge through the parallel section. In the Fig. 2 timing diagram, the key is to synchronize the charge output timing with the timing of the output serial register. This is achieved by combining the transfer gates of the conventional parallel to output serial register and that of the output serial register gate.

This is achieved by the structure illustrated in Fig. 3. Fig. 3 shows the layout of the...