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PLA with Threshold Logic

IP.com Disclosure Number: IPCOM000045470D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Giuliani, SW: AUTHOR [+2]

Abstract

ROMs (read-only memories) utilizing three-state and four-state cells are known in the art. The object thereof is to store more information in a given silicon area. This article describes a scheme to realize similar advantages with PLA (programmable logic array), a density gain of about 50-100%. The following assumptions are made: A. A process is employed to provide three different kinds of diodes with distinct turn-on voltages. Word lines and bit lines are interconnected by one or none of these diodes. Each intersection may be regarded as a four-state cell. Symbol Device Turn-on voltage (H) High Barrier Schottky VDH approx. 0.8 V Barrier Diode (M) PN Junction Diode VDM approx. 0.6 V (L) Low Barrier Schottky VDL approx. 0.4 V B.

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PLA with Threshold Logic

ROMs (read-only memories) utilizing three-state and four-state cells are known in the art. The object thereof is to store more information in a given silicon area. This article describes a scheme to realize similar advantages with PLA (programmable logic array), a density gain of about 50-100%. The following assumptions are made:

A. A process is employed to provide three different kinds of diodes with distinct turn-on voltages. Word lines and bit

lines are interconnected by one or none of these

diodes. Each intersection may be regarded as a

four-state cell.

Symbol Device Turn-on voltage

(H) High Barrier Schottky VDH approx. 0.8 V

Barrier Diode

(M) PN Junction Diode VDM approx. 0.6 V

(L) Low Barrier Schottky VDL approx. 0.4 V

B. A word line driver (WLD) is available. Three binary signals input into the WLD driver which outputs to the word line

four possible distinct voltage levels (according to whether

any input or which input is activated). See Figs. 1A

and 1B.

C. A pair of binary signals, Proportional to Beta, are partitioned in a decoder which

provides four signals: Proportional to Beta, Proportional

to Beta, Proportional to Beta, Proportional to Beta. These

signals serve as inputs to the WLD.

D. Bit lines are normally Down. They are pulled up if a diode is turned on by a selected word line. The pulled Up level is

detected by a sense amplifier. Bit lines will serve as

product terms in the AND array, and as outputs in the OR

array.

The bit line output is to be interpreted as a logic function of the input pair Proportional to Beta. The function is determined by the personalization of the cell...