Browse Prior Art Database

Contact Hole Process Improvement for Silicon Gate Products

IP.com Disclosure Number: IPCOM000045473D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Chanclou, R: AUTHOR [+3]

Abstract

At the end of the FET manufacturing process when an SiO(2) phosphosilicate glass (PSG) composite passivation layer is used, it might be desirable to etch contact holes through this passivation layer until the substrate is exposed.

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Contact Hole Process Improvement for Silicon Gate Products

At the end of the FET manufacturing process when an SiO(2) phosphosilicate glass (PSG) composite passivation layer is used, it might be desirable to etch contact holes through this passivation layer until the substrate is exposed.

When a standard photolithography step involving photoresist masking is used, the holes present a very steep profile which will be subsequently the source of many reliability problems (cracks, cuts in the metallurgy, etc.). Such a steep profile is illustrated in Fig. 1.

It has been recognized that some previous heat treatments, in the course of semiconductor processing, have altered the superficial portion of the overlying PSG layer, making the latter denser and harder; hence the PSG layer will act as a blocking mask for the underlying SiO(2) layer.

The problem may be overcome by removing the top surface of the PSG layer by a flash etch (buffered HF etch, diluted HF or plasma etch) prior to depositing the photoresist masking layer. Fig. 2 shows the new improved profile of the opening thus obtained.

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