Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Anaylsis Tool for Logic Cards with Integrated Module

IP.com Disclosure Number: IPCOM000045474D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 118K

Publishing Venue

IBM

Related People

Begasse, P: AUTHOR

Abstract

This tool is designed for testing 48-pin modules. It uses a multiprobe to contact the module pins. Logic state storage, comparison and indication are provided for analysis purposes.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Anaylsis Tool for Logic Cards with Integrated Module

This tool is designed for testing 48-pin modules. It uses a multiprobe to contact the module pins. Logic state storage, comparison and indication are provided for analysis purposes.

As shown in Fig. 1A, probe 1 is connected through multiplexed analog switches to comparators COMP 1 and COMP 2, which perform comparisons with a positive reference voltage and a negative reference voltage, respectively. The comparison results are stored, through Shift register SM REG 1, in a memory MEM or a register REG. The memory data associated with the register data switch ON or OFF 48 light-emitting diode (LED) indicators.

PROCESS. After the module pins are contacted by the probe, the operator depresses the reset switch SW 1. This starts the process. The tester is in the "loop option mode until first error". At each error detection, the comparison result is logged in 8-bit shift register 1. After 8 intervals which correspond to the checking of 8 pins, are counted by counter CTR, the shift register data are stored in the memory, and 6-bit shift register SH REG 2 shifts one bit. This shift register selects another multiple analog switch and a new memory address.

This operation is resumed for a new module with another rotary switch selection.

For comparison, the process is the same as described above, but data from register SH REG 1 are stored in a register REG, the contents of which will be compared with the memory data. In this case, the first error will be changed by a forced error.

OPERATOR PROCEDURE. The tester indicates the bad card I/O pins. The operator checks the module's used pin. During loop processing, the op...