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Browse Prior Art Database

Staggered Circuit Switching

IP.com Disclosure Number: IPCOM000045482D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

Very large-scale integration (VLSI) permits up to several thousand circuits being arranged on a single silicon chip. As a result of the internal structure of a logic thus designed, a plurality of circuits, belonging to subgroups A to D of the entire chip logic, as well as synchronously clocked gates and line drivers are simultaneously switched. This leads to relatively high power dissipation which adversely affects the operating speed of the circuits.

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Staggered Circuit Switching

Very large-scale integration (VLSI) permits up to several thousand circuits being arranged on a single silicon chip. As a result of the internal structure of a logic thus designed, a plurality of circuits, belonging to subgroups A to D of the entire chip logic, as well as synchronously clocked gates and line drivers are simultaneously switched. This leads to relatively high power dissipation which adversely affects the operating speed of the circuits.

To improve the operating speed of such logic structures, a higher performance must be provided and the power dissipation involved be acceptable to the semiconductor chip. When master/slave latches are used, for example, one way of accomplishing this is to stagger the] A- and B-clock pulses applied to subgroups A to D of the logic (Fig. 1). These staggered clock pulses are designated as A1, B1 to A4, B4 (see also Figs. 2 and 3).

This does not affect the synchronism of the logic but leads to a staggered operation of the logic subgroups. The time units Dt of the stagger must be of minimum length but be sufficient to avoid too many circuits being simultaneously switched. This necessitates that the staggered time pulses are generated very accurately, which is difficult owing to unpredictable delay tolerances caused by tolerances of the production parameters of the chips.

To solve this problem, a clock adjust circuit (Fig. 2) is provided for comparing the generated A- and B-clock pulses with reference clock pulses REFA and REFB which are also generated by...