Browse Prior Art Database

Multioscillator Dynamic Processor Operation

IP.com Disclosure Number: IPCOM000045483D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

In multiprocessing systems, processing units, produced by different technologies and thus having different internal propagation delays, may have to communicate. Such communication is effected through asynchronous buses, using known two- or three-wire handshake mechanisms for data transfer.

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Multioscillator Dynamic Processor Operation

In multiprocessing systems, processing units, produced by different technologies and thus having different internal propagation delays, may have to communicate. Such communication is effected through asynchronous buses, using known two- or three-wire handshake mechanisms for data transfer.

Processing units PU 1 and PU 2 in Fig. 1 are data processing units with different internal propagation delays, whose internal functional data flow operates at different clock speeds which are generated at frequencies fI and fII by two independent oscillators (OSC I, OSC II) 3 and 4. The use of two oscillators permits the processors to be operated at their maximum speed.

For communicating with PU 2, PU 1 transfers the information destined for PU 2 by a bus 6 at clock frequency fI. PU 2 asynchronously receives this information at clock frequency fII. Thus, this conventional method necessitates synchronizing an interface signal of PU 1 according to the clock scheme of PU 2. Such synchronization is necessary for each information transfer during an interface operation and may be effected by the conventional handshake mechanism which, compared to a synchronous interface, involves the transfer of additional handshake control signals.

To prevent the operating speed of such systems being impaired in that way, it is proposed that the asynchronous handshake mechanism be replaced by a synchronous deskewed clock transfer scheme. However, a synchronous deskewed clock transfer scheme necessitates that the two communicating units are operated by pulses from a common (synchronous) clock pulse generator.

For this purpose, the clock pulses from oscillator 4 to PU 2 are also transferred to PU 1 to generate synchronous clock pulses at the interface of the common bus. However, the internal data flow 5 of PU 1 is not synchronous with bus interface 17, as the two components are controlled by different clock oscillators. To avoid this asynchronism, the following is proposed.

After a bus-oriented instruction has been decoded in PU 1, clcck pulse generation for internal data flow 5 is controlled by os...