Browse Prior Art Database

Terminal Response Time Monitor

IP.com Disclosure Number: IPCOM000045506D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Ziecina, FJ: AUTHOR

Abstract

Computer system requirements for terminal response times are stated as times and percentiles. A response time specification may state that the terminal responses must be less than 2.5 seconds 90 percent of the time. A circuit for enabling such measurements is shown above. The terminal (not shown) has an input-inhibited lighted indicator which can be sensed by a photosensitive element 1 to determine whether the input-inhibited indicator is on or off. The input-inhibited indicator is on during the time the computer system is processing a terminal request.

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Terminal Response Time Monitor

Computer system requirements for terminal response times are stated as times and percentiles. A response time specification may state that the terminal responses must be less than 2.5 seconds 90 percent of the time. A circuit for enabling such measurements is shown above. The terminal (not shown) has an input-inhibited lighted indicator which can be sensed by a photosensitive element 1 to determine whether the input-inhibited indicator is on or off. The input- inhibited indicator is on during the time the computer system is processing a terminal request.

The output of the photosensitive element 1 is applied as an input to edge detect circuit 2. This circuit generates a pulse on the start line when the input- inhibited indicator turns on. A pulse on the start line increments transaction counter 3 and loads timer 4 with a value represented by the setting of switches 5. The timer 4 consists of counters that count down. The value set into timer 4 from switches 5 is the acceptable time limit. This time normally is in terms of seconds and tenths of a second.

Timer 4 is driven by a clock 6 via AND circuit 10. AND circuit 10 is conditioned by the output of inverter 11 which is fed by the output of AND circuit
7. AND circuit 7 has an output when the value in the counter of timer 4 goes to zero. Thus, AND circuit 10 will pass the pulses from clock 6 until the counter of timer 4 is decremented to a value of zero.

The output of inverter 11 also...