Browse Prior Art Database

Virtual Address Translation Registers

IP.com Disclosure Number: IPCOM000045508D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 45K

Publishing Venue

IBM

Related People

Kirby, JB: AUTHOR

Abstract

The logical address for addressing main storage can be expanded into a larger real address by using address translation registers such as described In U. S. Patent 4,093,986. This type of address translation is schematically illustrated in Fig. 1 where the 5 high-order bits of the logical address select 1 of 32 address translation registers which provide 8 high-order bits of the real address. This address translation arrangement is satisfactory, but when the size of real main storage is increased, the number of address translation registers required also increases if the offset, i.e., the page size, remains the same.

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Virtual Address Translation Registers

The logical address for addressing main storage can be expanded into a larger real address by using address translation registers such as described In
U. S. Patent 4,093,986. This type of address translation is schematically illustrated in Fig. 1 where the 5 high-order bits of the logical address select 1 of 32 address translation registers which provide 8 high-order bits of the real address. This address translation arrangement is satisfactory, but when the size of real main storage is increased, the number of address translation registers required also increases if the offset, i.e., the page size, remains the same.

It is desirable to keep the page size the same in order to use the same control programming when the size of main storage has been increased on a computer system or when a new computer system has been designed with a larger main storage and can use an existing operation system. Additionally, it can be shown that there can be both a performance improvement and a reduction in hardware by providing virtual address translation registers instead of keeping all the address translation registers in hardware.

Instead of keeping all the address translation registers in hardware, a limited number are kept in hardware and a virtual address translation register access table (VATRAT) is used to specify whether or not an instruction is referencing a hardware address translation register or one which is in main storage. If an instruction references an address translation register that is in main storage, the execution of the instruction is temporarily halted until the address translation register in main storage is transferred into the hardware address translation register in the central processing unit.

The VATRAT is then updated accordingly.

The virtual address translation register arrangement could improve the performance of the computer system set forth in U.S. Patent 4,093,986 because all of the address translation registers (ATRs) are loaded after every task switch. Thus, if a limited number of hardware address translation registers are used, the overhead of loading these registers after every task switch would be reduced. The virtual address translation register arrangement requires only one hardware address translation register in order to function, but more may be added for performance reasons.

The prior address translation registers' method, i.e., that of
U. S. Patent 4,093,986, is schematically illustrated in Example 1.

In Example 1 there are 32 hardware ATRS 12. These registers are loaded with data from storage 15. The registers 12 are accessed by control logic in the virtual address translation register access control (VATRAC) block 100 which receives the high-order 5 bits of the logical address. In this and the following examples, the following definitions and equations apply: DEFINITIONS
PSPACE = Program address SPACE (e.g. , 64k on IBM System/34) PSIZE = Page SIZE (e.g., 2k on S/...