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Variable Length, Variable Count, Shift Right Instruction

IP.com Disclosure Number: IPCOM000045510D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Kirby, JB: AUTHOR

Abstract

The shift right instruction is found in most computer system; however, some computer systems when addressing operands address the rightmost byte. This creates a problem when it is desired to treat all instructions in the computer system consistently, i. e., using a common addressing arrangement. The problem with using the rightmost byte first when performing a shift right instruction is that there is no bit available to be shifted into the rightmost byte. The operation of a shift right instruction where the leftmost byte of the operand is addressed first is schematically illustrated in Fig. 1. The leftmost byte of a three-byte operand in main storage 10 is addressed by an address in storage address register (SAR) 20 and read into shift register 30.

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Variable Length, Variable Count, Shift Right Instruction

The shift right instruction is found in most computer system; however, some computer systems when addressing operands address the rightmost byte. This creates a problem when it is desired to treat all instructions in the computer system consistently, i. e., using a common addressing arrangement. The problem with using the rightmost byte first when performing a shift right instruction is that there is no bit available to be shifted into the rightmost byte. The operation of a shift right instruction where the leftmost byte of the operand is addressed first is schematically illustrated in Fig. 1. The leftmost byte of a three- byte operand in main storage 10 is addressed by an address in storage address register (SAR) 20 and read into shift register 30. The byte in shift register 30 is then shifted one bit to the right, and the bit shifted out of shift register 30 is stored in one-bit register 40. The address in SAR 20 is incremented whereby a second byte of the operand in main storage 10 is addressed and read from storage into shift register 30. This time when the shift operation is performed, the bit from register 40 is entered into the high-order position of shift register 30 and the low- order bit in shift register 30 is shifted out into one bit register 40. The operation continues until all bytes of the operand have been read from storage and shifted one bit to the right.

The present arrangement for solving the problem is schematically illustrated in Fig. 2, whereby the number of bytes to be shifted is subtracted from the operand address before the data is shifted. The conventional way to perform this subtraction would be to use the arithmetic unit of the processor. This would, however, add five cycles to every shift right instruction and would take five control logic states because the number of bytes to be...