Browse Prior Art Database

Enhanced Concurrency Using a Multilevel Cache System

IP.com Disclosure Number: IPCOM000045559D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

Current high level processors are limited by cache bandwidth. Using the approach described below, bandwidth within the hierarchy removes this limitation.

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Enhanced Concurrency Using a Multilevel Cache System

Current high level processors are limited by cache bandwidth. Using the approach described below, bandwidth within the hierarchy removes this limitation.

Conventional memory hierarchies utilize the bandwidth between the levels only to satisfy misses from levels in the hierarchy above it. However, if the processor does not force all its accesses to be honored at the highest level. the bandwith of the lower levels can deliver additional operands to requesting units, allowing them to process concurrently. Since all cache levels are supersets of the levels above them and all cache levels maintain directories, an access to a lower level which is serviced directly can be performed subsequent to a castout/invalidation of the higher level, as required.

A trivial example of the above in a two-level hierarchy, as shown in the figure, is to honor I-accesses from the L1 and data accesses from the L2. Store in I cache is prevented by bits maintained in the L2 directory.

Another example is to process certain VFL/DEC (variable field length/decimal) operands directly from the L2 (special E-Units) while honoring all other accesses from the L1.

In a three-level hierarchy operating system, macros (dispatch, trace, lock) may be Processed in the L3 while the other levels function as above.

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