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Mechanisms for Decentralized Bandwidth Allocation in Inter-Processor Communication Facilities

IP.com Disclosure Number: IPCOM000045564D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 5 page(s) / 85K

Publishing Venue

IBM

Related People

Calo, SB: AUTHOR [+3]

Abstract

A system is described herein for allocating time slots to particular processors connected to a common time-division-multiplexed channel which are requesting service. The system differs from certain known systems in that once a time slot in a frame is assigned, it remains assigned to the processor until the job is terminated. See Fig. 1.

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Mechanisms for Decentralized Bandwidth Allocation in Inter-Processor Communication Facilities

A system is described herein for allocating time slots to particular processors connected to a common time-division-multiplexed channel which are requesting service. The system differs from certain known systems in that once a time slot in a frame is assigned, it remains assigned to the processor until the job is terminated. See Fig. 1.

Each processor in the system is connected to the common data bus via an adapter. In operation, when an associated processor requests a time slot, the adapter selects an arbitrary "unassigned" time slot and interrogates a separate "contention line" to see if that slot is being used. If not, the adapter places a lock bit on the contention line for that slot and the processor proceeds to transmit during the particular time slot (each frame) until the message is fully transmitted, at which time the slot is reallocated to the system.

In order to understand the system, it is necessary first to describe briefly the nature of the communications bus and associated terminology.

The communications bus is a synchronous parallel time-multiplexed bus. Data is transmitted in byte-parallel mode on 8 data lines; 16 bytes constitute a packet. The time taken to transmit a packet on the bus is called a slot; 256 slots constitute a synchronous frame (Fig. 2). Slots are numbered 0 through 255 within a frame. Contention for the allocation of the (i+1)st slot always takes place during the ith slot period. Contention for slots takes place independently on a separate line, called the contention line. Thus, the contention process and data transmission are completely overlapped.

Those adapters which have been commanded to contend for a given slot do so by driving the contention line at specific times. These specific times correspond to the byte transmission times on the data lines. Thus, a maximum of 16 "drive-times" are available to the adapters (Fig. 3).

A preferred mechanism (M1) for accomplishing the required system control involves a three-part hardware modification of the communication adapter and a software module resident in each of the processors in the system. The first part of the hardware modification is as follows: the adapter provides for a 256-bit register (called the Slot Allocation Register (SAR)) which stores the slot numbers allocated to that adapter. Thus, for example, if bit n in the SAR is a one, it indicates that the adapter may transmit during the nth slot period without contention. We propose that the contents of the SAR be allowed to drive the contention line during one of the four "drive-times" which are at present unused. It is immaterial which one of the four is chosen. We shall refer to this "drive-time" as the A/D (allocated/ deallocated) bit. During the i-th slot period within a synchronous frame, (for i=0 through 255) the value of the i-th bit in the SAR is gated to the A/D bit on the contention line....