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LSSD Compatible Divide by N Counter

IP.com Disclosure Number: IPCOM000045573D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Canova, FJ: AUTHOR [+3]

Abstract

This "divide-by-N" counter is a binary frequency divider which is particularly suitable where "N" is a relatively small number. "N" may be either an odd number or an even number. This counter employs level sensitive scan design (LSSD)-type shift register latches (SRLs) and hence is fully compatible with the LSSD design philosophy which is described in Eichelberger et al., "A Logic Design Structure for LSI Testability". 14th Design Automation Conference Proceedings, 462-467 (June 1977).

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LSSD Compatible Divide by N Counter

This "divide-by-N" counter is a binary frequency divider which is particularly suitable where "N" is a relatively small number. "N" may be either an odd number or an even number. This counter employs level sensitive scan design (LSSD)-type shift register latches (SRLs) and hence is fully compatible with the LSSD design philosophy which is described in Eichelberger et al., "A Logic Design Structure for LSI Testability". 14th Design Automation Conference Proceedings, 462-467 (June 1977).

The ability to divide the input frequency from an oscillator by any number of divisions, especially odd numbers, is often needed. In an LSSD design, the implementation of a frequency divider can be costly in logic circuit overhead due to the requirements of the LSSD design ground rules. The counter mechanism described herein enables the designer to implement hardware to easily match his required output frequency to that of a fixed number of input oscillator frequencies. This mechanism also optimizes the logic circuit overhead for small divider networks while completely adhering to the LSSD design ground rules.

Fig. 1 shows a "divide-by-two" counter. This counter includes a pair of polarity-hold latches L1 and L2 which make up a so-called SRL in an LSSD circuit design. During normal frequency dividing operations, the SRL scan mode A and B clocks are inactive (both are zero) and the C clock is active. During this normal operation, the circuit operates to divide the frequency of the oscillator (OSC) input signal by a factor of two, the desired output signal being available at the + L2 output of the L2 latch. The oscillator signal as applied to the B clock input of the L2 latch is inverted in phase relative to the oscillator signal supplied to the C clock input of the L1 latch. This phase inversion is provided by the OR circuit 3. The out-of-phase output of the L2 latch is supplied back by way of a delay circuit 4 to the data (D) input of the L1 latch. This delay circuit 4 includes two single input logic gates connected in series to provide two circuit units of delay in the feedback path. This delay insures glitchless operation during the clock transition when both the L1 and L2 latche...