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Multi-Purpose Half Adder

IP.com Disclosure Number: IPCOM000045597D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Bula, J: AUTHOR [+2]

Abstract

Half-adder circuits are traditionally composed of two exclusive OR circuits feeding a NAND circuit together with a suitable inverter circuit to produce the odd and the even bits. These stages are then replicated a sufficient number of times to generate the desired half adder. This article discloses that a single exclusive OR and a NAND can be used to produce the even bit while a single exclusive OR together with an inverter can be used to provide the odd bit.

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Multi-Purpose Half Adder

Half-adder circuits are traditionally composed of two exclusive OR circuits feeding a NAND circuit together with a suitable inverter circuit to produce the odd and the even bits. These stages are then replicated a sufficient number of times to generate the desired half adder. This article discloses that a single exclusive OR and a NAND can be used to produce the even bit while a single exclusive OR together with an inverter can be used to provide the odd bit.

Thus, Fig. 1 illustrates the circuit designed to produce the even bit in the half- adder circuit. Devices 10, 11 and 12 are all depletion devices, while devices 13 through 19 are enhancement devices. Devices 10, 11, 13, 14, 15, 16, and 17 together comprise an exclusive OR, while devices 12, 18, and 19 form a NAND circuit.

The odd bit circuit shown in Fig. 2 is similarly formed with devices 21, 22 and 23 being depletion transistors and devices 24 through 29 being enhancement devices. In this case, devices 22, 23, 25, and 26, 27, 28, and 29 form an exclusive OR and the devices 21 and 24 form an inverter circuit.

The inputs for the even bit circuit are Ao and Co, while its outputs are So and C1. The inputs for the odd bit circuit are C1 and A1, while its outputs are S1 and C2.

The input and output combination for each circuit is summarized in the following truth tables. Even Bit Odd Bit

Ao Co So C1 A1 C1 S1 C2

0 0 0 1 0 0 1 0

0 1 1 1 0 1 0 0

1 0 1 1 1 0 0 1

1 1 0 0 1 1 1 0

1

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