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Bipolar Dynamic Random Access Memory Cell

IP.com Disclosure Number: IPCOM000045599D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chesebro, DG: AUTHOR [+4]

Abstract

A bipolar dynamic random-access memory cell having interconnected PNP and NPN transistors is fully isolated by a dieiectric medium and cludes an enhanced storage capacitor. A cell of this type is described in U.S. Patent 4,309,716.

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Bipolar Dynamic Random Access Memory Cell

A bipolar dynamic random-access memory cell having interconnected PNP and NPN transistors is fully isolated by a dieiectric medium and cludes an enhanced storage capacitor. A cell of this type is described in U.S. Patent 4,309,716.

As shown in the figure, an N type semiconductor substrate 10 has formed thereon a thin layer 12 of dielectric material, preferably silicon dioxide, and a layer of single crystal N type silicon 14. The single crystal silicon layer 14 and the dielectric layer 12 may be made by any known method, such as disclosed in U.
S. Patent 3,919,060 or in IBM Technical Disclosure Bulletin 24, 11A. 5458-5459 (April 1982).

First and second P type diffusion regions 16 and 18 are formed in silicon layer 14 and an N type diffusion region 20 is forced within P type diffusion region
16. Regions 16 and 20 and layer 14 form the NPN transistor, and regions 16 and 18 and layer 14 form the PNP transistor.

Trenches 22 are formed through silicon layer 14 and silicon dioxide layer 12 into substrate 10. The walls and bottom of trenches 22 are oxidized to form silicon dioxide layers 24. The trenches 22 are then filled with any suitable dielectric material 26, such as silicon dioxide. If desired, after etching silicon dioxide layer 24 from the bottom of trenches 22, trenches 22 may be filled with doped N type polysilicon or with a single crystal semiconductor grown from substrate 10.

The cell is completed by providing suitabl...