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JFET Threshold Voltage Adjusting Circuit

IP.com Disclosure Number: IPCOM000045602D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Atwood, BC: AUTHOR

Abstract

A circuit is provided for controlling the gate threshold voltage of a junction field-effect transistor (JFET) which has an NPN and PNP transistor feedback to the bottom gate of the JFET.

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JFET Threshold Voltage Adjusting Circuit

A circuit is provided for controlling the gate threshold voltage of a junction field-effect transistor (JFET) which has an NPN and PNP transistor feedback to the bottom gate of the JFET.

Fig. 1 is a layout of a known annular JFET, and Fig. 2 is d sectional view of the JFET taken through line 2-2 of Fig. 1. N- type epitaxial layer 10, formed on P type semiconductor substrate 12, is the bottom gate of the JFET, and annular N+ region 14, formed in a P type pocket 16, is the top gate.

Note that current through the JFET channel is decreased as more positive voltages are applied to the gates. For a given bottom gate voltage, the threshold voltage is defined as tie top gate voltage that cuts off the channel current. A higher voltage applied to the bottom gate results in a lower threshold voltage at the top gate.

The JFET threshold voltage is adjusted by the circuit shown in Fig. 3 which has a feedback circuit connected to the bottom gate 10 of JFET J shown in Figs. 1 and 2.

In the operation of the circuit of Fig. 3, if the threshold voltage of JFET J is higher than the voltage Vref, about 1.5 to 3 volts, minus the base-emitter voltage Vbe of NPN transistor T1, JFET J is on and current flows to the base of Tl, turning on Tl and thus also PNP transistor T2. Current flow through T2 increases the voltage across resistor R, causing the voltage on bottom gate 10 of JFET J to increase which decreases current flow between the source and...