Browse Prior Art Database

Test Structure for Measuring Isolation Sheet Resistance

IP.com Disclosure Number: IPCOM000045628D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Nyborg, CA: AUTHOR

Abstract

With the advent of VLSI, high density arrays are forcing isolation walls between memory cells to be as narrow as minimum ground rules will permit and the voltage drop in the different isolation return paths can be significant. This article describes a test structure which can help circuit designers to monitor the isolation sheet resistance in order to accurately calculate this drop.

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Test Structure for Measuring Isolation Sheet Resistance

With the advent of VLSI, high density arrays are forcing isolation walls between memory cells to be as narrow as minimum ground rules will permit and the voltage drop in the different isolation return paths can be significant. This article describes a test structure which can help circuit designers to monitor the isolation sheet resistance in order to accurately calculate this drop.

The drawings show in a plan view (Fig. 1) and a cross-section (Fig. 2) a test structure to measure the end-of-process isolation sheet resistance. Mask levels are indicated in Fig. 1 as follows: A - subcollector mask; B - isolation mask; C - collector reach-through mask; D - recessed oxide isolation mask; E - base diffusion mask; and F - contact mask. Kelvin contacts are used to limit the voltage drop to between the inner edges of the two current-forcing pads designated I1 and 12.

Basically, the structure consists of a rectangular P+ isolation diffusion (ISO) indicated by a B-mask surrounded by an N+ diffused subcollector with an N diffused EPI layer and a final recessed oxidation isolation (ROI) on top to make the isolation ring complete.

As all current paths between the two isolation diffusion pads terminate a few tenths of a micron below the isolation surface, the substrate underneath (P-) will not contribute to the current flow.

The subcollector-to-isolation spacing should be large enough to prevent an intersected subcollector isolation junction (8-10 Um), and the width of the isolation diffusion should be large enough to minimize the effect of B-mask image tolerance (30-40 Mum).

As the isolation diffusion is essentially buried below a layer of ROI, the current-forcing pads I1, I2 can be made minimum size (75 Mu m x 75 Mum) and be placed di...