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Parallel To Serial Data Transfer in an Interlaced SPS CCD Memory

IP.com Disclosure Number: IPCOM000045635D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Carballo, RA: AUTHOR [+3]

Abstract

This is a serial-parallel-serial charge-coupled device (SPS-CCD) memory with an improved serial-to-parallel data transfer. The CCD loop architecture described uses a four-gate two-phase design which can be easily extended to a multiplexed N-electrode per bit configuration by increasing the number of clocks in the parallel section of the array. Both double polysilicon (DPS) and triple polysilicon (TPS) structures are described.

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Parallel To Serial Data Transfer in an Interlaced SPS CCD Memory

This is a serial-parallel-serial charge-coupled device (SPS-CCD) memory with an improved serial-to-parallel data transfer. The CCD loop architecture described uses a four-gate two-phase design which can be easily extended to a multiplexed N-electrode per bit configuration by increasing the number of clocks in the parallel section of the array. Both double polysilicon (DPS) and triple polysilicon (TPS) structures are described.

The key feature in the design is the improved single gate output transfer connected to the BOUT clock which greatly enhances the loop performance and reduces the overall physical dimensions of the SPS structure. However, greater improvements can be achieved by using a third polysilicon gate from a triple polysilicon process added to the charge transfer stages of both the input and output registers. This design is useful for both surface channel and buried channel CCDs.

Fig. 1A is a top view and Fig. 1B is a cross-sectional view of the parallel-to- serial transfer structure implemented in DPS. Referring first to Fig. 1B, P type substrate 10, first polysilicon layer P1, second polysilicon layer P2, and recessed oxide isolation 12 are formed by known processes. For example, it is known that a field implant (not shown) is required under oxide 12. Fig. 1B is a section along line X' in Fig. 1A.

In Fig. 1A, clock terminal VST is connected to the indicated P1 (POLY 1) and P2 (POLY 2) Polysilicon Rates. The 0OUT clock terminal is connected to the second P2 gate. The 01 and 02 clock terminals are each connected to successive P1 and P2 gate pairs in the serial output register. Hence, the two- phase/four-gate output configuration. It is noted that the input serial-to-parallel charge transfer is accomplished with a similar stru...