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ROS Bit Line Ground Clamp

IP.com Disclosure Number: IPCOM000045664D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Mahlbacher, MH: AUTHOR [+2]

Abstract

The circuit shown in Fig. 1 clamps bit lines in a read-only store (ROS) array to ground until they are selected in the manner of a set/reset latch. When the line is unselected, a field-effect transistor (FET) to ground of relatively low current and high threshold is gated on. FETs gated on to select the bit line have zero-volt thresholds, and the signal passing through them overpowers the first FET. The circuit accelerates the periodic discharges of the bit line.

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ROS Bit Line Ground Clamp

The circuit shown in Fig. 1 clamps bit lines in a read-only store (ROS) array to ground until they are selected in the manner of a set/reset latch. When the line is unselected, a field-effect transistor (FET) to ground of relatively low current and high threshold is gated on. FETs gated on to select the bit line have zero- volt thresholds, and the signal passing through them overpowers the first FET. The circuit accelerates the periodic discharges of the bit line.

In a typical operation of a ROS, most of the bit lines are unselected and left floating at a preset voltage level. Changes in voltage on these lines are caused by substrate voltage fluctuations, noise on the bit lines, and other external influences. Such changes can be sufficient to change the logic state of an associated sense amplifier, thus giving a false read-out. The bit line clamp circuit presented here eliminates this hazard. An advantage of this clamp circuit is that it can be placed on either end of the bit line, which facilitates layout on a solid- state substrate. Further, since most of the bit lines are unselected, the circuit operates in a natural mode in which zero power is dissipated for all but the selected lines.

The clock and restore signals are shown along a time reference in Fig. 2. FETs T1 and T2 have zero threshold levels (natural threshold). During the restore pulse, the clock is at ground. Bit line 1 is discharged to ground through FET T3, an enhancement-mode device, when the restore pulse rises past the threshold of FET...