Browse Prior Art Database

Parity Checking

IP.com Disclosure Number: IPCOM000045669D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

This is a method of parity checking of logic where a single fault may cause an even number of errors among the outputs for which a parity is generated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Parity Checking

This is a method of parity checking of logic where a single fault may cause an even number of errors among the outputs for which a parity is generated.

Sometimes, a single fault in the FUNCTION GENERATOR logic (single stuck fault) may produce an even number of errors among the outputs X1 through XM. The PARITY GENERATOR would then wrongly produce a correct generated parity, PGX, and no error would be detected.

To overcome this condition, additional predicted parities are produced for comparison with corresponding generated parities. The additional parities are selected to cover even errors (resulting from single faults) that have been missed by the ODD ERROR signal. These parities need not be carried along in parallel with the FUNCTION GENERATOR outputs, so that they may be implemented with more gate levels and fewer gates.

Fig. 1 illustrates the use of these additional parities. The

FUNCTION GENERATOR produces a byte of output signals X0 through X7, while the PARIM PREDICT produces the predicted parity PPX, as before.

Assume that some single stuck faults produce an even number of errors in output combinations (X0, X1), (X2, X3), (X4, X5), (X6, X7), and (X4 X5, X6, X7). To check for these even errors, additional parity predIct signals are produced for the pairs of FUNCTION GENERATOR outputs (X0, X4), (X1, X5), (X2, X6), and (X3, X7) from inputs I1 through IN. Corresponding generated parities, (X0, X4), (X1, X5), (X2, X6), and (X3, X7), derived from...