Browse Prior Art Database

Electronic Chip in Place Testing Arrangement for Clock Signals

IP.com Disclosure Number: IPCOM000045672D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Das Gupta, S: AUTHOR [+2]

Abstract

The structure described in the following paragraphs will allow clocks and data signals on a chip 10 to be treated equivalently. Thus, all chip inputs are treated alike during test generation and testing, and complete isolation of the chip logic from that for other chips for testing purposes is obtained.

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Electronic Chip in Place Testing Arrangement for Clock Signals

The structure described in the following paragraphs will allow clocks and data signals on a chip 10 to be treated equivalently. Thus, all chip inputs are treated alike during test generation and testing, and complete isolation of the chip logic from that for other chips for testing purposes is obtained.

Both clock and data inputs are fed to L2* latches 12 Each clock or data input 14 has a corresponding dummy input 16. These dummy inputs 16 are driven from Pads on modules or internal test points on cards. During normal operation, the dummy inputs 16 are disabled. During testing, the clock input 14 and the test clock signal enable clock signals to be sent to the chip from the tester through dummy inputs 16. Note that with this structure, the scan clock L1 and L2 latches are all gated by L2 latches that they scan. Problems caused by this are solved by connecting the latches on chip I/Os into a separate scan ring 18. Now by shifting this ring 18 first, these chip I/O latches can be set to the proper value such that scan clocks can be provided to the scan ring for the SRLs (shift register latches) in the system logic. Thus, two scan sequences are required per test.

Since the I/O scan ring 18 is operated separately from the system SRL scan ring 20, common scan-in/scan-out pins 22 can be used for both scan rings. At the second level of the package the scan-out of one chip serves as the scan-in of the next ch...