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Supporting Additional Channels on a Uniprocessor by Channel Set Switching

IP.com Disclosure Number: IPCOM000045675D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Biersack, FP: AUTHOR [+4]

Abstract

This article describes how a single central processor system (i.e., uniprocessor (UP) can use plural channel sets in order to enable a UP to extend the number of channels it can support. The UP uses channel set interrupts in the manner defined in a prior article (F. P. Biersack, L.S. DeOrsey, A. S. Meritt and P. J. Wanish, "Removing CPU Affinity for I/O via Channel Set Switching, IBM Technical Disclosure Bullentin 24, 2346,2347 (October 1981).)

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Supporting Additional Channels on a Uniprocessor by Channel Set Switching

This article describes how a single central processor system (i.e., uniprocessor (UP) can use plural channel sets in order to enable a UP to extend the number of channels it can support. The UP uses channel set interrupts in the manner defined in a prior article (F. P. Biersack, L.S. DeOrsey, A. S. Meritt and
P. J. Wanish, "Removing CPU Affinity for I/O via Channel Set Switching, IBM Technical Disclosure Bullentin 24, 2346,2347 (October 1981).)

The IBM System/370 architecture permits only one channel set to be connected to a central processor at any time. There is a future architectural limit of 32 channels per channel set, since the control register used for masking contains only 32 bits. In addition, many operating systems support a maximum of 16 channels per channel set. Thus, there is an inherent limit of 32 (or 16) channels that can be supported on a uniprocessor.

Channel-set switching does permit management of multiple channel sets, thus extending the number of channels that can be attached. However, as currently defined, it has some practical disadvantages in providing the capability to have more than 32 channels per processor, or more than 16 channels per processor within the current operating restrictions. This is because only one channel set can be connected to a processor at a time.

To address this, the operating system could leave all channel sets disconnected and connect to whichever one was necessary for the purpose of issuing an I/O instruction; after the instruction was issued, the channel set could be disconnected. However, I/O inter...