Browse Prior Art Database

Memory System Reliability Enhancement by Module Swapping

IP.com Disclosure Number: IPCOM000045676D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Cecchi, DR: AUTHOR

Abstract

It can be advantageous to obtain semiconductor memory modules for computer systems from vendors as off the shelf items, i.e., to the vendor's own specifications. Because the memory modules are to the vendor's specifications there is an exposure to high failure rates. Reliability of a memory system can be improved hy incorporating better detection and correction into the system. Double-error detection and single-error correction is usually not cost prohibitive. However, to provide greater reliability, such as by incorporating double error correction circuitry, the cost becomes significant. The present arrangement provides improved memory system reliability without significantly increasing the cost.

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Memory System Reliability Enhancement by Module Swapping

It can be advantageous to obtain semiconductor memory modules for computer systems from vendors as off the shelf items, i.e., to the vendor's own specifications. Because the memory modules are to the vendor's specifications there is an exposure to high failure rates. Reliability of a memory system can be improved hy incorporating better detection and correction into the system. Double-error detection and single-error correction is usually not cost prohibitive. However, to provide greater reliability, such as by incorporating double error correction circuitry, the cost becomes significant. The present arrangement provides improved memory system reliability without significantly increasing the cost. Spare memory modules are provided on the memory card together with a switching network used to substitute a spare module for a module determined to be bad. The testing and substitution process can be accomplished at initial program load time or during normal operation utilizing programming invoked by detection of an error.

In Fig. 1, two spare bits are used as backup for a single data bit. The switching of the spare bits into the system is under control of latches N1 and N2. The right path for the memory system with a single spare bit is shown in Fig. 2. Fig. 3 shows an implementation where the entire module is swapped. Additional logic can be used to substitute a spare module for the normal module on a block basi...