Browse Prior Art Database

Extending an Instruction Set to Allow Additional Index Registers

IP.com Disclosure Number: IPCOM000045678D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Whitely, LD: AUTHOR

Abstract

A mechanism is provided which allows the use of previously defined work registers as address register consistent with an existent instruction set such as one used in the IBM System/3 and System/34 computer systems. The expanded register set is shown in Fig. 1. The Q-codes to support operations on these registers are likewise expanded, one Q-code indicating a two-byte operation and the other indicating a three-byte operation. Any register used to address an operand has its address specified in two of the first four bits in the op code. Once the code points are used up, there is no provision for expansion of index registers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Extending an Instruction Set to Allow Additional Index Registers

A mechanism is provided which allows the use of previously defined work registers as address register consistent with an existent instruction set such as one used in the IBM System/3 and System/34 computer systems. The expanded register set is shown in Fig. 1. The Q-codes to support operations on these registers are likewise expanded, one Q-code indicating a two-byte operation and the other indicating a three-byte operation. Any register used to address an operand has its address specified in two of the first four bits in the op code. Once the code points are used up, there is no provision for expansion of index registers.

The problem is solved by the addition of an extended op code (XOP) (Fig. 2) to the instruction set that would, when used, change the meaning of the already present addressing selection bits in the op register and provide additional bits to assist in addressing the new work registers as index registers. This provides an additional twelve address registers, bringing the total available to fourteen.

The hardware will always set XOP to '11001100'b at the beginning of the instruction fetch cycle and that particular bit combination will indicate that the original definitions in OP are in force, as shown in Fig. 3. When XOP(2 3 6 7)='0000'b, the definition of OP(01 2 3) remains unchanged. If, however, XOP(2 3)='00'b, then XOP(2 3) is catenated with OP(0 1) to form the LSR (local storage register) address from which the appropriate register for calculating the storag...