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Parity Checking of PLA Implemented Counter

IP.com Disclosure Number: IPCOM000045685D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Boden, RC: AUTHOR [+2]

Abstract

Fig. 1 illustrates symbolically an 8-stage binary counter withone parity stage, implemented in a conventional programmable logic array (PLA) comprising an AND array 10 and an OR array 11.

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Parity Checking of PLA Implemented Counter

Fig. 1 illustrates symbolically an 8-stage binary counter withone parity stage, implemented in a conventional programmable logic array (PLA) comprising an AND array 10 and an OR array 11.

Logically, AND array 10 comprises a plurality of AND-gates. Each word line symbolizes one multi-input AND-gate, so that, in Fig. 1, the AND array 10 comprises twelve AND-gates. The inputs of each of these AND-gates correspond to vertical lines extending from the respective numbered lines in the signal path labelled "Feedback Path". Two complementary input lines, that is, O and 1, are provided from each stage. A 1 digit at the intersection of a word line row and an input line column symbolizes that the 1 input line is connected to one input of the AND-gate, a O character designates a 0 input line Is connected to one input terminal of the AND-gate, and a "dot" indicates that no connection is made to the AND-gate at that point. Word line 4 in Fig. 1 symbolizes, for example, a three Input AND-gate involving the 1 input line from feedback paths 5, 6 and 7.

The outputs of the AND-gates are gated in parallel to the OR array by a clock pulse designated C in Fig. 1.

The OR array 11 logically comprises a plurality of bistable devices and a plurality of multi-input OR-gates. As shown in Fig. 1, nine "toggle"-type devices are symbolized in output block 14 by stages O through P. Since toggle-type devices logically require only one input, the OR array comprises one OR-gate for each stage in the output. The logical connection of the output of the AND-gates in array 10 to the inputs of the OR-gates in array 11 is symbolized by the character T at the appropriate row and column intersection. For example, the output of the five input AND-gate symbolized by word line 6 is connected o the OR-gate symbolized by character T corresponding to output stage 2. Therefore, logically, the bistable device of stage 2 will be toggled when stages 3, 4, 5, 6 and 7 are all at a 1 value and a clock pulse gates the output of the AND-gate to the OR array 11. The bistable devices may be on the same integrated circuit chip as the OR and AND arrays or on separate chips. Parity is maintained in this typical counter by the section labelled "Parity Predict Section" which requires the use of four AND-gates (word lines 9-12) in addition to those required for the counter itself.

Fig. 2 illustrates how the...