Browse Prior Art Database

System Reset Protection Synchronous Cache System Destaging

IP.com Disclosure Number: IPCOM000045687D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Anderson, RW: AUTHOR [+4]

Abstract

This invention relates to a method for inhibiting the SYSTEM RESET INTERRUPTION by a CPU of DASD (direct-access storage device) to cache destaging within a storage subsystem initiated by another CPU in a multi-CPU shared access storage subsystem environment. The method includes locking a hardware path to the second CPU for the destaging duration and queueing of the system reset.

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System Reset Protection Synchronous Cache System Destaging

This invention relates to a method for inhibiting the SYSTEM RESET INTERRUPTION by a CPU of DASD (direct-access storage device) to cache destaging within a storage subsystem initiated by another CPU in a multi-CPU shared access storage subsystem environment. The method includes locking a hardware path to the second CPU for the destaging duration and queueing of the system reset.

When a cache update operation is performed by the attaching channel, a hierarchical DASD storage subsystem will be disconnected from the channel to perform a destage function, i.e., to put back the updated data from the cache to the disk track. The cache storage subsystem will initiate an internal seek and set sector to the proper track for data to be updated. Once the channel is disconnected from the storage director, the interface channel switch is returned back to the neutral position. This will allow the storage director and the channels to start polling sequences and to allow a new start I/O.

Once the internal seek and set sector are done, an interrupt causes the reconnection of the device to the storage director without a channel being connected. Even though the hardware is primed with control unit busy if any start I/O is initiated from any channel, however, the system reset can be issued to the caching storage director from any attaching host channels. The standard control unit mechanism is not able to protect the caching storage director from being hit by the system reset. Therefore, the destaging activity will be abruptly terminated. Note, system reset issued while the channel switch of the storage director is in neutral position will force the microcode instruction address to a predetermined reference (default) location. This abrupt termination of the destaging activity will leave the channel, which the storage director owed allegiance to, in a limbo state. The channel is still in disconnected state waiting for a device-end status from the storage director to reconnect and continue execution of the unfinished channel program. The foregoing can be avoided by the following measures:

When the cache storage director is in disconnected state and detects the interrupt from the drive due to the completion of the internal seek and set sector, the storage director will do the following to protect itself from being reset by a system reset coming from any channel except the one it...