Browse Prior Art Database

Multi Level Logic Testing

IP.com Disclosure Number: IPCOM000045698D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Hayward, M: AUTHOR

Abstract

A two-state logic array buried behind a multi-level logic input block on a complex integrated circuit module has heretofore been tested using special test pins providing access to the logic array, with the multi-level logic being separately tested using analogue methods. A macro equivalence scheme allows a single test procedure to be applied to both the two-state logic array and the multi-level logic input block. By this means, logic simulation and pattern generation can be applied to the input port of the module, saving the special test pins and avoiding time-consuming testing with two testers.

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Multi Level Logic Testing

A two-state logic array buried behind a multi-level logic input block on a complex integrated circuit module has heretofore been tested using special test pins providing access to the logic array, with the multi-level logic being separately tested using analogue methods. A macro equivalence scheme allows a single test procedure to be applied to both the two-state logic array and the multi-level logic input block. By this means, logic simulation and pattern generation can be applied to the input port of the module, saving the special test pins and avoiding time-consuming testing with two testers.

The block diagram of Fig. 1 shows a portion of a typical integrated circuit module 1 to which this technique can be applied. In this example, the module carries a two-state logic array 2 buried behind multi-level logic 3 and accessed from input port 4. A number of individual devices 5.1 to 5.n are connected to port 4 in a multi-drop configuration. The operation protocol of the circuit demands that only one device be active at a sample time, and the circuit described tests for this condition. Each device, when active, draws a defined current k from the module. The number of currents nk, where n=0, 1, 2 ....., is detected on the
module. Three possibilities, namely, n=0, n=1, or n=2, need to be considered.

Two comparators 6.1 and 6.2 within the multi-level input block 3, supplied respectively with appropriately valued references REF 1 and REF 2, provide a partial logical resolution inasmuch as an output from comparator 6.1 indicates the condition n=1 and an output from comparator 6.2 indicates the condition n >/= 2...