Browse Prior Art Database

Improved Dual Sensitivity TDI Imaging Device

IP.com Disclosure Number: IPCOM000045723D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Schlig, ES: AUTHOR

Abstract

This article describes a novel, economical, high performance implementation of the one-stage/all-stage dual sensitivity feature for a CCD (charge-coupled device) imaging device.

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Improved Dual Sensitivity TDI Imaging Device

This article describes a novel, economical, high performance implementation of the one-stage/all-stage dual sensitivity feature for a CCD (charge-coupled device) imaging device.

The present CCD imaging device includes a surface-channel CCD array of 1024 32-stage imaging and integrating registers (parallel array), a parallel to serial CCD interface and a 1024-stage buried channel CCD serial register divided into 8 128-stage sections with 8 output ports. Time Delay Integration (TDI) CCD imaging arrays are known in the combination of structure and applied signals.

Farrier and Dyck (*) bring out only one "exposure control" electrode separately per reduced sensitivity level (as in the present invention) but, since all parallel clocks run normally for all sensitivity modes, they use a higher-potential down-level on the parallel clock signals than on the exposure-control electrode signal. This has certain disadvantages:
1. For a given on-chip voltage range, the signal charge capacity

and consequently the signal to noise ratio is reduced.
2. Photoelectrons collected in the unused part of the parallel

array must diffuse to a drain against the directionality

of the parallel clock. To do this, a charge distribution

along each parallel channel must be created, the amplitude

of which determines the diffusion current. The amplitude

is restricted to the difference in down-levels between the

parallel clocks and the exposure control electrode

signal. This low amplitude restricts the diffusion current

and thus the saturation input light flux in this mode.
3. The two different down levels complicates the drive circuitry.

Other multiple sensitivity TDI arrays are in the literature, but the means of implementation are not detailed.

A straightforward way of avoiding the disadvantages cited above would be to supply separate clock signals to each section of the parallel array so the clocks supplied to the unused sections can be either run backwards or held at their high level while the clocks supplied to the used sections are run normally. This has the disadvantage of increasing the number of clock connections and clock signals supplied to the parallel array.

In our particular case of i...