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Parallel Adapter for a Logic Simulation Machine

IP.com Disclosure Number: IPCOM000045729D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Kronstadt, EP: AUTHOR [+3]

Abstract

A plurality of randomly occurring signals are each applied to n different slot processors to be assembled for transmission in parallel to a logic simulation device. The identical processors, termed slot processors, each include an instruction memory and share a common control logic for controlling the transmission of the assembled bits to the logic simulator.

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Parallel Adapter for a Logic Simulation Machine

A plurality of randomly occurring signals are each applied to n different slot processors to be assembled for transmission in parallel to a logic simulation device. The identical processors, termed slot processors, each include an instruction memory and share a common control logic for controlling the transmission of the assembled bits to the logic simulator.

A number of uses of a logic simulation machine (LSM) require a high bandwidth parallel port into the part of the machine that is running the simulation. Some examples are: 1. A general parallel probe attachment to the LSM for hardware

emulation.

2. Parallel port for direct driving of high speed peripherals.

3. Parallel port for attaching array simulators.

The following describes the structure of a high bandwidth Parallel Data attachment (PAD) to support these kinds of LSM enhancements.

The major features of the PAD as outlined are:

1. High bandwidth, over 90 Mbytes total, inbound and outbound.

2. Easy compiler scheduling.

3. Direct control of attached device's control lines.

4. Little additional hardware to implement the features set

forth above.

The PAD, as set forth in Fig. 1, consists of two independent sections, the first section 2 controlling outbound transfers and the second section 4 controlling inbound transfer. each section consists of 17 identical processors 6 called slot processors or SP's. Each section has an instruction memory (IM) 8, and both sections share some common control logic 10.

Outbound Data Flow. The outbound data flow depicting one slot processor and the common logic is shown in Fig. 2.

The main operation of the SP is straightforward:

1. The SP is simply a dual-port memory. On the ith instruction

cycle the data from the switch is written into the ith

memory location. During each cycle the instruction memory

8 applies a unique read address to every SP memory read

port, and passes the read word on the outbound lines.

2. On a given instruction cycle if there is a data word to be

read by the external device, the IM8 issues a data ready

signal which loads the output register 12 and causes the

control to initiate an external write cycle.

3. The opcode bits on line 14 are a vector of sixteen

uninterpreted bits that can be used by the PAD to issue

commands to the attached device, or to instruct the

attached device how to interpret the word on the output

lines.

1

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Inbound Data Flow. The inbound data flow is quite similar to the outbound. The operation of the inbound SP is...