Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

True/Complement NMOS Rich CMOS Logic Circuit

IP.com Disclosure Number: IPCOM000045781D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+3]

Abstract

A true/complement logic circuit is provided which is of a static form and substantially noise, such as proportional to - particle, insensitive. The circuit is made in complementary metal oxide semiconductor (CMOS) technology having only three P channel devices, with the remaining devices being N channel transistors (NMOS).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

True/Complement NMOS Rich CMOS Logic Circuit

A true/complement logic circuit is provided which is of a static form and substantially noise, such as proportional to - particle, insensitive. The circuit is made in complementary metal oxide semiconductor (CMOS) technology having only three P channel devices, with the remaining devices being N channel transistors (NMOS).

As indicated in the figure, with the voltage at terminal S low, P channel transistor P1 turns on and N channel transistor N2 and P channel transistor P2 turn on, while N channel transistor N1 and P channel transistor P3 are turned off. Thus, the voltage at output node 0 is high and the voltage at the output node 0 is low. When the voltage at terminal S goes high, N1 turns on and Pl turns off; however, P2 remains on due to the positive feedback connection between node 0 and the control gate of P2.

If the vectorial input I(n) causes the NMOS combinatorial network to conduct, node 0 is pulled low enough to turn on P3 which drives output node 0 to a high voltage, turning off P2 and latching output node 0 to its low state.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]