Browse Prior Art Database

Three Way Exclusive or Circuit

IP.com Disclosure Number: IPCOM000045782D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

This logic circuit provides an exclusive-OR (XOR) function of three variables combined into one logic block with improved density, performance and power.

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Three Way Exclusive or Circuit

This logic circuit provides an exclusive-OR (XOR) function of three variables combined into one logic block with improved density, performance and power.

As indicated in the circuit of Fig. 1, transistor N1 is an N channel depletion device and all other transistors are N channel enhancement devices. If desired, transistor N1 may be replaced by any suitable current source.

It can be seen that the voltage at the output is high only when the voltage at only one of the control gates A, B or C is high or when the voltage at all of the gates A, B and C is high. In all other instances the voltage at the output will be low. Accordingly, the XOR function is ABC + ABC + ABC + ABC. For example, if B is high and A and C are low, thus B is low and A and C are high, it should be noted that transistor N3 is off and, although transistor N2 is on, the output is high since it is isolated from ground by transistors NS and N9 being turned off.

This exclusive-OR circuit may be used in, e.g., addition, multiplication or parity circuits. The circuit of Fig. 2 shows an arrangement of four of these exclusive-OR circuits interconnected to form a nine-bit parity circuit.

It should be noted that if inputs A and A in Fig. 1 are interchanged, an XOR function is obtained.

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