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Voltage Level Transfer Driver Circuits

IP.com Disclosure Number: IPCOM000045785D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Lee, H: AUTHOR [+2]

Abstract

A driver circuit is provided wherein the low level at the output terminal is clamped at a predetermined intermediate level between the supply voltage and ground potential.

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Voltage Level Transfer Driver Circuits

A driver circuit is provided wherein the low level at the output terminal is clamped at a predetermined intermediate level between the supply voltage and ground potential.

In the operation of the circuit of Fig. 1, when the voltage at the input terminal is, say, +8.5 volts minus a threshold voltage V(T), transistors T1 T2 and T3 are on and transistors T4 and T5 are off. Thus, the voltage at the output is high, i.e., at +8.5 volts minus the threshold voltage, V(T3), of transistor T3. As the input voltage drops to zero volts, transistors T1, T2 and T3 turn off and transistors T4 and T5 turn on, causing charge sharing to occur between the output terminal and capacitor C, resulting in the output voltage initially discharging to below +5 volts minus the threshold voltage V(T6) of transistor T6 and then stabilizing at +5 volts minus V(T6). It can be seen that this circuit provides a non-inverted output voltage.

In Fig. 2, when the voltage at the input terminal is at zero volts, transistors T1, T4 and T5 are off and transistors T2 and T3 are on. Thus, the voltage at the output is high, i.e., at +8.5 volts minus the threshold voltage V(T6) of transistor T6 and minus the threshold voltage V(T3) of transistor T3. When the input voltage increases to +8.5 volts minus a threshold voltage V(T), transistors T1, T4 and T5 turn on and transistors T2 and T3 turn off, causing charge sharing to occur between the output terminal and capacitor C,...