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Distributed Directory Enhanced Array

IP.com Disclosure Number: IPCOM000045806D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 29K

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Wassel, ER: AUTHOR


The arrangement herein disclosed makes it possible to decrease cache access time at a modest increase in cost.

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Distributed Directory Enhanced Array

The arrangement herein disclosed makes it possible to decrease cache access time at a modest increase in cost.

A typical cache subsystem can be organized at present as shown in Fig. 1. A main storage address is presented to the directory and cache array. Note that only a small number of address lines are needed for the array selection, while the balance of the lines are used by the directory. One function of the directory is to match the higher-order address bits to its contents, and then provide the balance of the array address.

This type of organization has proven to be a cost-effective technique for implementing a cache subsystem. It is circuit efficient, and assumes multiple chip crossings are not detrimental.

As increased chip densities have evolved, chip crossings have begun to represent a disproportionate amount of cycle time. One technique for improving system performance is to reduce signal path length by minimizing chip crossings. With increased circuit density, it is possible to economically reorganize, redistribute, and even replicate system function.

As shown in Fig. 2, the main directory does not participate in the array selection during a normal cache access. This reduces the signal path and access time. An on-chip (local) directory address match function is provided by logic placed on each array chip to handle the address(es) of its data contents. The precise implementation is determined by the array configurat...