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Scan Loadable Mode Registers for Multiple Processor, Multiple Architecture Systems

IP.com Disclosure Number: IPCOM000045807D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Callahan, RW: AUTHOR [+2]

Abstract

Mixed processor and/or architecture systems are known. In such systems, it would be advantageous to allow the master or service processor to control or reconfigure each processor, as required, in order that the system may achieve high availability and versatility. The main objectives of this capability are: 1. to gain high availability by allowing a service/master processor to turn off a failing processor and turn on a redundant processor or subunit, 2. to allow a service/master processor to instruct a failing 32 bit address architecture Processor to switch to 24-bit architecture and continue running if the failure occurred in the high-order addressing, and 3.

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Scan Loadable Mode Registers for Multiple Processor, Multiple Architecture Systems

Mixed processor and/or architecture systems are known. In such systems, it would be advantageous to allow the master or service processor to control or reconfigure each processor, as required, in order that the system may achieve high availability and versatility. The main objectives of this capability are: 1. to gain high availability by allowing a service/master processor to turn off a failing processor and turn on a

redundant processor or subunit, 2. to allow a service/master processor to instruct a failing 32 bit address architecture Processor to switch to 24-bit

architecture and continue running if the failure occurred

in the high-order addressing, and 3. to allow a service/master processor in a multi-processor/multiple architecture system to reconfigure

any processor to run under a different architecture simply by

running a different microcode emulator.

To achieve these objectives, the system is provided with a plurality of mode resisters. Loading of each mode register is accomplished by the service/master processor via the respective service/ master bus interface (SBI), as shown in Fig.
1. The service/master processor treats each mode register as a separate scan string. The mode registers control on/off status of their respective processors, which microcode emulator they run, 32-bit or 24-bit architecture, and other functions deemed necessary by the designers. See Fig. 2 for...