Browse Prior Art Database

Selective Filling of Isolation Trenches in Silicon

IP.com Disclosure Number: IPCOM000045811D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Mutter, WE: AUTHOR

Abstract

Deep trench isolation is an attractive way of providing electrical insulation between adjacent elements on an integrated circuit chip. Lithography and reactive ion etching (RIE) techniques have developed to a Point where trenches 1.5-micrometer wide and 3- or 4-micrometer deep can beroutinely produced in silicon. The problem is to fill these trenches with something to provide a planar surface for chip wiring and to provide electrical isolation. Trenches have been filled with thermally grown silicon dioxide. chemical vapor deposited SiO(2), polysilicon, glass, etc. All these methods not only fill the trench but also cover the entire surface of the wafer with a thick layer of fill material which must subsequently be removed.

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Selective Filling of Isolation Trenches in Silicon

Deep trench isolation is an attractive way of providing electrical insulation between adjacent elements on an integrated circuit chip. Lithography and reactive ion etching (RIE) techniques have developed to a Point where trenches
1.5-micrometer wide and 3- or 4-micrometer deep can beroutinely produced in silicon. The problem is to fill these trenches with something to provide a planar surface for chip wiring and to provide electrical isolation. Trenches have been filled with thermally grown silicon dioxide. chemical vapor deposited SiO(2), polysilicon, glass, etc. All these methods not only fill the trench but also cover the entire surface of the wafer with a thick layer of fill material which must subsequently be removed.

The present technique uses electrostatic forces to guide charged, sub-micron particles of fill material selectively into the trench where they are discharged and adhere. The principles of the method are similar to those employed in the well- developed field of xerography. Various methods of selective charging and selective filling or development are possible.

A silicon wafer 10 with trenches 12 is shown in Fig. 1. The wafer 10 has a silicon dioxide layer 14 on the wafer surface and bare silicon in the trenches 12. A negative charge may be placed on the surface oxide by grounding the wafer and passing a corona brush discharge over the surface. If this wafer is now exposed to an aerosol of negatively charged fill particles, the particles w...