Browse Prior Art Database

Precision Sidewall Technology

IP.com Disclosure Number: IPCOM000045812D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Riseman, J: AUTHOR [+3]

Abstract

The insulator sidewall can be formed by depositing a first layer 10, such as polycrystalline silicon, onto a substrate 11. Lithography and anisotropic etching form substantially vertical sidewalls on the layer 10, as shown in Fig. 1. A first insulator layer 12, such as silicon dioxide, is uniformly deposited over layers 10 and 11. A second layer 13, such as silicon nitride or polycrystalline silicon, has the etching characteristic that it etches more slowly in the subsequent reactive ion etching ambient than the first insulating layer 12. The thickness of the first layer 12 is, for example, 400 nanometers, and the second layer 13 is less than 50 nanometers.

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Precision Sidewall Technology

The insulator sidewall can be formed by depositing a first layer 10, such as polycrystalline silicon, onto a substrate 11. Lithography and anisotropic etching form substantially vertical sidewalls on the layer 10, as shown in Fig. 1. A first insulator layer 12, such as silicon dioxide, is uniformly deposited over layers 10 and 11. A second layer 13, such as silicon nitride or polycrystalline silicon, has the etching characteristic that it etches more slowly in the subsequent reactive ion etching ambient than the first insulating layer 12. The thickness of the first layer 12 is, for example, 400 nanometers, and the second layer 13 is less than 50 nanometers. Since the anisotropy of the reactive ion etch (RIE) gives about a 20 to 1 slower etch rate of the vertical to the horizontal surface, a 50- nanometer film of Si(3)N(4) would be removed but only 1/20 x (50.0)=2.5 nanometers of the vertical Si(3)N(4) would be removed. The result of this process is shown in Fig. 2. The RE which hd been selected to etch SiO (2) preferentially to Si(3)N(4), will then attack and etch the SiO(2) at a rate equivalent to about 4 to 1. Including the horizontal to vertical etch rate differential, the horizontal plane of SiO(2) will therefore etch at about 20/1 times 4/1 that of the vertical Si(3)N(4), or an etch bias of about 80/1. Thus, a 400- nanometer film of SiO(2) would be removed, but only about the 1/80 x 400- nanometer equivalent of Si(3)N(4) or abou...