Browse Prior Art Database

Method for forming N+ - P+ Tunnel Junctions

IP.com Disclosure Number: IPCOM000045824D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Campbell, DR: AUTHOR [+2]

Abstract

Tunnel diodes are useful for making high speed random-access memories and logic, specially if they can be integrated with high speed silicon NPN bipolar technologies. The process described is particularly suited for such applications because of its compatibility with the conventional NPN bipolar process and negligible additional heat cycles.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Method for forming N+ - P+ Tunnel Junctions

Tunnel diodes are useful for making high speed random-access memories and logic, specially if they can be integrated with high speed silicon NPN bipolar technologies. The process described is particularly suited for such applications because of its compatibility with the conventional NPN bipolar process and negligible additional heat cycles.

After completion of all the process steps to form the collector 12 and P isolation 11 in P- substrate 10, N epitaxial layer 13, base 14 and emitter 16 of the NPN transistor in any desired manner, but before metallization, the following additional steps are taken to fabricate the tunnel diode.
1. Use a photoresist mask to open a window 18 in the P- base

region of the NPN transistor, as shown in the figure by

etching away the thermal reoxidation silicon dioxide layer 20

which covers all the contact openings at this stage.
2. Diffuse boron to form a P++ layer 28 near She surface of

window 18. Impurity concentration of about 5 x 10/19/

atoms/cm(3) or more is needed for strong tunneling

action. Alternately, ion implant; boron through the

silicon dioxide layer 2O and anneal to achieve the same end

result. The original silicon dioxide and silicon

nitride layers 22 and 24, respectively, should then be

sufficiently thick to prevent significant implant into

regions outside the window 18. Note that the photoresist

layer covers all the wafer except areas close to the window

18 during this step.
3. Strip photoresist, if used.
4. Use silicon sputter etch - sputter deposition to pre-clean

the exposed silicon surface in window 18, followed by

sputter deposition of several tens of nanometers of amorphous

silicon. This operation can be carried out at as low a

temperature as about 100 degrees C, and, as such, contributes

little to the total heat cycle of the process.
5. Implant arsenic at about 5 KeV to 25 KeV to confine the

implant to within the amorphous silicon. Note that in-situ

doped silicon can be used instead of undoped silicon followed

by implantation.
6. Use a masking step to etch away the silicon layer from

everywhere <except over the window 18.
7. Deposit a film of near noble metal, such as platinum or

palladium. Its thickness should...